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? 2011 microchip technology inc. ds41189b-page 1 rfhcs362g/362f general ? combination k ee l oq ? encoder and synthesized uhf ask/fsk transmitter in a single package ? operates on a single lithium coin cell - <200 na typical standby current - 4.8 to 11.5 ma transmit current - 2.2 to 5.5v operation ? integrated solution with minimum external parts ? separate pin-outs for k ee l oq encoder and rf transmitter provides for design flexibility code hopping encoder ? programmable minimum code word completion ? battery low signal transmitted to receiver with pro- grammable threshold ? non-volatile eeprom storage of synchronization data ? easy to use eeprom programming interface ? pwm or manchester modulation ? selectable encoder data rate 417 to 3334 bps ? on-chip tunable encoder oscillator ? rf enable output for transmitter control ? button inputs have internal pull-down resistors ? elapsed time and button queuing options ? current limiting on led output ? 2-bit crc for error detection uhf ask/fsk transmitter ? conforms to us fcc part 15.231 regulations and european erc 70-03e and en 300 220-1 requirements ? vco phase locked to quartz crystal reference; allows narrow receiver bandwidth to maximize range and interference immunity ? crystal frequency divide by 4 output (clkout) ? transmit frequency range (310 ? 440 mhz) set by crystal frequency ? ask modulation ? fsk modulation through crystal pulling (RFHCS362F) ? adjustable output power: -12 dbm to +2 dbm ? differential output configurable for single or double ended loop antenna ? automatic power amplifier inhibit until pll lock pin diagrams security ? programmable 28/32-bit serial number ? two programmable 64-bit encryption keys ? programmable 60-bit seed ? each 69-bit transmission is unique with 32 bits of hopping code ? encryption keys are read protected applications ? automotive remote keyl ess entry (rke) systems ? automotive alarm systems ? automotive immobilizers ? community gate and garage door openers ? identity tokens with usage counters ? burglar alarm systems ? building access device features encrypt keys encoding transmitter rfhcs362ag 2 x 64 pwm/man ask rfhcs362af 2 x 64 pwm/man ask/fsk soic v ss s2 xtal s3/rfen out v dd led /shift s1 rfen in clkout ps/data ask v ddrf s0 lf 2 3 4 5 6 7 8 9 ?1 17 16 14 13 12 11 10 15 18 rfhcs362g data ant2 nc v ssrf ant1 ssop v ss s2 data fsk s3/rfen out v dd led /shift s1 rfen in clkout ps/data ask v ddrf s0 lf 2 3 4 5 6 7 8 9 ?1 19 18 16 15 14 13 12 17 20 RFHCS362F data nc v ssrf ant2 ant1 10 11 fsk out xtal k ee l oq ? code hopping encoder with uhf ask/fsk transmitter
rfhcs362g/362f ds41189b-page 2 ? 2011 microchip technology inc. 1.0 general description the rfhcs362g/362f is a code hopping encoder plus uhf transmitter designed for secure wireless com- mand and control systems. the rfhcs362g/362f uti- lizes the k ee l oq ? code hopping technology which incorporates high security in a small package outline at a low cost to make this device well suited for unidirec- tional remote keyless entr y systems and access control systems. the rfhcs362g/362f combines a 32-bit hopping code generated by a nonlinear encryption algorithm with a 28/32-bit serial number and 9/ 5 status bits to create a 69-bit transmission stream. the length of the transmis- sion strongly resists the th reat of code scanning. the code hopping mechanism makes each transmission unique, thus rendering code capture and resend (code grabbing) schemes virtually useless. the encryption key, serial number and configuration data are stored in an eepr om array which is not accessible via any external connection. the eeprom data is programmable but read protected. the data can be verified only after an autom atic erase and program- ming operation. this protects against attempts to gain access to keys or manipulate synchronization values. the rfhcs362g/362f provides an easy to use serial interface for programming the necessary keys, system parameters and configuration data. the transmitter is a fully integrated uhf ask/fsk transmitter consisting of crystal oscillator, phase- locked loop (pll), open-collector differential-output power amplifier (pa), and mo de control logic. external components consist of bypass capacitors, crystal, and pll loop filter. there are no internal electrical connec- tions between the encoder and the transmitter. the encoder oscillator is independent from the transmitter crystal oscillator. the rfhcs362g is capable of amplitude shift keying (ask) modulation by turning the pa on and off. the RFHCS362F is capable of ask or frequency shift key- ing (fsk) modulation by employing an internal fsk switch to pull the transmitter crystal via a second load capacitor. the rfhcs362g/362f is a single channel device. the transmit frequency is fixed and set by an external refer- ence crystal. transmit frequencies in the range of 310 to 440 mhz can be selected. output drive is an open- collector differential amplifier. the differential output is well suited for loop antennas. output power is adjust- able from +2 dbm to -12 dbm in six discrete steps. the rfhcs362g/362f are radio frequency (rf) emit- ting devices. wireless rf devices are governed by a country?s regulating agency. for example, in the united states it is the federal communications committee (fcc) and in europe it is the european conference of postal and telecommunica tions administrations (cept). it is the responsibility of the designer to ensure that their end product conforms to rules and regulations of the country of use and/or sale. rf devices require correct board level implementation in order to meet regulatory requirements. layout con- siderations are given in section 6.0 uhf ask/fsk transmitter. 1.1 important terms the following is a list of key terms used throughout this data sheet. for additional information on k ee l oq and code hopping refer to technical brief 3 (tb003). ? rke - remote keyless entry ? button status - indicates what button input(s) activated the transmission. encompasses the 4 button status bits s3, s2, s1 and s0 (figure 3-6). ? code hopping - a method by which a code, viewed externally to the system, appears to change unpredictably each time it is transmitted. ? code word - a block of data that is repeatedly transmitted upon button activation (figure 3-6). ? transmission - a data stream consisting of repeating code words (figure 10-1). ? encryption key - a unique and secret 64-bit number used to encrypt and decrypt data. in a symmetrical block cipher such as the k ee l oq algorithm, the encryption and decryption keys are equal and will be referred to generally as the encryption key. ? encoder - a device that generates and encodes data. ? encryption algorithm - a recipe whereby data is scrambled using a encryption key. the data can only be interpreted by the respective decryption algorithm using the same encryption key. ? decoder - a device that decodes data received from an encoder. ? decryption algorithm - a recipe whereby data scrambled by an encryption algorithm can be unscrambled using the same encryption key. ? learn ? learning involves the receiver calculating the transmitter?s appropriate encryption key, decrypting the received hopping code and storing the serial number, synchronization counter value and encryption key in eeprom. the k ee l oq product family facilitates several learning strate- gies to be implemented on the decoder. the fol- lowing are examples of what can be done. - simple learning the receiver uses a fixed encryption key, common to all components of all systems by the same manufacturer, to decrypt the received code word?s encrypted portion.
? 2011 microchip technology inc. ds41189b-page 3 rfhcs362g/362f - normal learning the receiver uses information transmitted during normal operation to derive the encryp- tion key and decrypt the received code word?s encrypted portion. - secure learn the transmitter is acti vated through a special button combination to tr ansmit a stored 60-bit seed value used to generate the transmitter?s encryption key. the receiver uses this seed value to derive the sa me encryption key and decrypt the received code word?s encrypted portion. ? manufacturer?s code ? a unique and secret 64- bit number used to generate unique encoder encryption keys. each encoder is programmed with a encryption key that is a function of the man- ufacturer?s code. each decoder is programmed with the manufacturer code itself. 1.2 applications the rfhcs362g/362f is suited for secure wireless remote control applications. the eeprom technology makes customizing application programs (transmitter codes, appliance settings, et c.) extremely fast and con- venient. the small footprint packages are suitable for applications with space limitations. low-cost, low- power, high performance, ease of use and i/o flexibility make the rfhcs362g/362f very versatile. typical application circuits are shown in figure 1-5 and figure 1-6. most low-end keyless entry transmitters are given a fixed identification code that is transm itted every time a button is pushed. the numbe r of unique identification codes in a low-end system is usually a relatively small number. these shortcomings provide an opportunity for a sophisticated thief to create a device that ?grabs? a transmission and retransmits it later, or a device that quickly ?scans? all possible identification codes until the correct one is found. the rfhcs362g/362f, on the other hand, employs the k ee l oq code hopping technology coupled with a trans- mission length of 66 bits to virtually eliminate the use of code ?grabbing? or code ?scanning?. the high security level of the rfhcs362g/362f is based on patented technology. a block cipher based on a block length of 32 bits and a key length of 64 bits is used. the algo- rithm obscures the information in such a way that even if the transmission information (before coding) differs by only one bit from that of the previous transmission, the next coded transmission will be completely differ- ent. statistically, if only one bit in the 32-bit string of information changes, approximately 50 percent of the coded transmission bits will change. figure 1-1: additional button inputs up to 7 button inputs can be implemented making them look like a binary value to the 3 sx inputs. this is done with switching diodes as shown in figure 1-1. the dis- advantage is that simultaneously pressed buttons now appear as if a single button is pressed. the rfhcs362g/362f has a small eeprom array which must be loaded with several parameters before use. these are most often programmed by the manu- facturer at the time of production. the most important of these are: ? a 28-bit serial number, typically unique for every encoder ? an encryption key ? an initial 16-bit synchronization value ? a 16-bit configuration value the encryption key generation typically inputs the transmitter serial number and 64-bit manufacturer?s code into the key generation algorithm (figure 1-2). the manufacturer?s code is chosen by the system manufacturer and must be care fully controlled as it is a pivotal part of the overall system security. the 16-bit synchronization counter is the basis behind the transmitted code word changing for each transmis- sion; it increments each time a button is pressed. due to the code hopping algorithm?s complexity, each incre- ment of the synchr onization value results in about 50% of the bits changing in the transmitted code word. v dd s0 s1 s2 rfen b4 b3 b2 b1 b0
rfhcs362g/362f ds41189b-page 4 ? 2011 microchip technology inc. figure 1-3 shows how the key values in eeprom are used in the encoder. once the encoder detects a button press, it reads the button inputs and updates the syn- chronization counter. the synchronization counter and encryption key are input to the encryption algorithm and the output is 32 bits of encrypted information. this data will change with every button press, its value appearing externally to ?randomly hop around?, hence it is referred to as the hopping portion of the code word. the 32-bit hopping code is combined with the button information and serial number to form the code word transmitted to the receiver. the code word format is explained in greater detail in section 3.1. a receiver may use any type of controller as a decoder, but it is typically a microcontroller with compatible firm- ware that allows the decoder to operate in conjunction with an rfhcs362g/362f based transmitter. section 7.0 provides detail on integrating the rfhcs362g/362f into a system. a transmitter must first be ?learned? by the receiver before its use is allow ed in the system. learning includes calculating the transmitter?s appropriate encryption key, decrypting the received hopping code and storing the serial number, synchronization counter value and encryption key in eeprom. in normal operation, each received message of valid format is evaluated. the serial number is used to deter- mine if it is from a learne d transmitter. if from a learned transmitter, the message is decrypted and the synchro- nization counter is verified. finally, the button status is checked to see what operation is requested. figure 1-4 shows the relationship between some of the values stored by the receiver and the values received from the transmitter. figure 1-2: creation and storage of encryption key during production transmitter manufacturer?s serial number code encryption key key generation algorithm serial number encryption key sync counter . . . rfhcs362 production programmer eeprom array
? 2011 microchip technology inc. ds41189b-page 5 rfhcs362g/362f figure 1-3: building the transmitted code word (encoder) figure 1-4: basic operation of receiver (decoder) note: circled numbers indicate the order of execution. button press information eeprom array 32 bits encrypted data serial number transmitted information encryption key sync counter serial number k ee l oq ? encryption algorithm button press information eeprom array manufacturer code 32 bits of encrypted data serial number received information decrypted synchronization counter check for match sync counter serial number k ee l oq ? decryption algorithm 1 3 4 check for match 2 perform function indicated by button press 5 encryption key
rfhcs362g/362f ds41189b-page 6 ? 2011 microchip technology inc. figure 1-5: ask example applications circuit
? 2011 microchip technology inc. ds41189b-page 7 rfhcs362g/362f figure 1-6: fsk example applications circuit
rfhcs362g/362f ds41189b-page 8 ? 2011 microchip technology inc. 2.0 device description the block diagram in figure 2-1 shows the internal configuration with the top ha lf representing the encoder and the bottom half the uhf transmitter. note that con- nections between the encoder and transmitter are made external to the device for more versability. typical application circuits are shown in figure 1-5 and figure 1-6. the rfhcs362g/362f requires only the addition of push button swit ches and few external com- ponents for use as a transmitter in your security appli- cation. see table 2-1 for pinout description. figure 2-2 shows the device i/o circuits. figure 2-1: rfhcs3 62 block diagram v ss v dd oscillator reset circuit led driver controller power latching and switching button input port 32-bit shift register encoder eeprom data led s3 s2 s1 s0 shift pll driver rfen rfen in divide by 4 mode control logic clkout power amplifier (pa) crystal oscillator ant2 ant1 xtal phase detector and charge pump voltage controlled oscillator (vco) fixed divide by 32 lf ps/data ask data fsk (1) fsk out (1) fsk switch v ddrf v ssrf note 1: RFHCS362F only.
? 2011 microchip technology inc. ds41189b-page 9 rfhcs362g/362f table 2-1: rfhcs362g/3 62f pinout description name soic pin # ssop pin # i/o/p type description ant1 10 11 o antenna connection to differential power amplifier output, open collector. ant2 9 10 o antenna connection to differential power amplifier output, open collector. clkout 6 7 o clock output. data 17 19 i/o encoder data output pin or serial programming. data fsk ? 15 i fsk data input. fsk out ? 16 o fsk crystal pulling output. led /shift 2 2 i/o current limited led driver. input sampled before led driven. lf 13 14 ? external loop filter conn ection. common node of charge pump output and vco tuning input. ps/data ask 7 8 i power select and ask data input. rfen in 5 6 i transmitter and clkout enable. internal pull-down. s0 3 3 i switch input 0 with internal pull-down. s1 4 4 i switch input 1 with internal pull-down. s2 15 17 i switch input 2 with internal pull-down or schmitt trigger clock input during serial programming. s3/rfen 16 18 i/o switch input 3 with inter nal pull-down or rf enable output as selected by rfen option in configuration word seed_3. v dd 1 1 p positive supply for encoder v ddrf 8 9 p positive supply for transmitter. v ss 18 20 p ground reference for encoder v ssrf 11 12 p ground reference for transmitter. xtal 14 5 i transmitter crystal connection to colpitts type crystal oscillator. legend: i = input, o = output, i/o = input/output, p = power
rfhcs362g/362f ds41189b-page 10 ? 2011 microchip technology inc. figure 2-2: i/o circuits 2.1 encoder architectural overview 2.1.1 onboard eeprom the rfhcs362g/362f has an onboard nonvolatile eeprom which is used to store user programmable data. the data can be programmed at the time of pro- duction and includes the security-related information such as encoder keys, seri al numbers, discrimination and seed values. all the security related options are read protected. the rf hcs362g/362f has built-in protection against counter corruption. before every eeprom write, the internal circuitry also ensures that the high voltage required to write to the eeprom is at an acceptable level. 2.1.2 internal rc oscillator the rfhcs362g/362f has an onboard rc oscillator that controls all the logic output timing characteristics. the oscillator frequency varies within 10% of the nominal value (once calibrated over a voltage range of 2v ? 3.5v or 3.5v ? 6.3v). all the timing values specified in this document ar e subject to the oscillator variation. figure 2-3: typical rfhcs362g/362f normalized oscillator period vs. temperature s0, s1, s2, rs inputs v dd rfen s3 input/ rs rdata data i/o led output rl rh v dd data ledh ledl rfen output pfet nfet pfet nfet nfet shift input shift rfen in nfet fsk out output ant1, ant2 outputs clkout v ddrf pfet nfet ps/data ask v ddrf v p ll lock 20 a v ddrf v vco 5 pf 200 200 change pump lf rfen in input xtal output ps data fsk input 0.94 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.92 0.90 v dd legend = 2.0v = 3.0v = 6.0v temperature c -50-40-30 -20 -10 0 10 20 30 40 50 6070 80 90 note: values are for calibrated oscillator
? 2011 microchip technology inc. ds41189b-page 11 rfhcs362g/362f 2.1.3 low voltage detector a low battery voltage detector onboard the rfhcs362g/ 362f can indicate when the operating voltage drops below a predetermined value. there are eight options available depending on the vlow [ 0..2 ] configuration options. the options provided are: figure 2-4: rfhcs362 v low detector (typical) figure 2-5: rfhcs362 v low detector (typical) the output of the low volt age detector is transmitted in each code word, so the decoder can give an indication to the user that the transmit ter battery is low. operation of the led changes as well to further indicate that the battery is low and needs replacing. 000 -2.0v 100 -4.0v 001 -2.1v 101 -4.2v 010 -2.2v 110 -4.4v 011 -2.3v 111 -4.6v 1.5 1.7 1.9 2.1 2.3 2.5 2.7 -40 -25 -10 5 20 35 50 65 80 v dd (v) temperature (c) v low option = 000 = 001 = 010 ? = 011 v dd (v) temperature (c) 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 -40 -25 -10 5 20 35 50 65 80 v low option = 100 = 101 = 110 ? = 111
rfhcs362g/362f ds41189b-page 12 ? 2011 microchip technology inc. 3.0 encoder operation the rfhcs362g/362f will wake-up upon detecting a switch closure and then delay for switch debounce (figure 3-1). the synchroni zation information, fixed information and switch information will be encrypted to form the hopping code. the encrypted or hopping code portion of the transmission will change every time a button is pressed, even if the same button is pushed again. keeping a button pressed for a long time will result in the same code word being transmitted until the button is released or time-out occurs. the time-out time can be selected with the time-out ( timout [ 0..1 ]) configuration option. this option allows the time-out to be disabled or set to 0.8 s, 3.2 s or 25.6 s. when a time-out occurs, the device will go into sleep mode to protect the battery from draining when a button gets stuck. if in the transmit process, and a new button is pressed, the current code word will be aborted. a new code word will be transmitted and the time-out counter will reset. if all the buttons are released, the minimum code words will be completed. the minimum code words can be set to 1, 2, 4 or 8 using the minimum code words ( mtx [ 0..1 ]) configuration option. if the time for trans- mitting the minimum code words is longer than the time-out time, the device will not complete the minimum code words. a code that has been transmitted will not occur again for more than 64k transmissions. this will provide more than 18 years of typical use before a code is repeated based on 10 operations per day. overflow information programmed into the encoder can be used by the decoder to extend t he number of unique trans- missions to more than 192k. figure 3-1: basic flow diagram of the device operation note: if multiple buttons are pressed and one is released, it will not have any effect on the code word. if no buttons remain pressed the minimum code words will be completed and the power-down will occur. start sample buttons increment seed time-out encrypt no no yes get config. tx? counter transmit mtx no buttons seed time read seed stop yes yes no yes no no ye s yes yes seed button no new buttons no no
? 2011 microchip technology inc. ds41189b-page 13 rfhcs362g/362f 3.1 transmission modulation format the rfhcs362 transmission is made up of several code words. each code word consists of a preamble, a header and data (see figure 3-2). the code words are separated by a guard time that can be set to 0 ms, 6.4 ms, 25.6 ms or 76.8 ms with the guard time select ( guard [ 0..1 ]) configuration option. all other timing specifications for the modulation formats are based on a basic timing element (t e ). this timing element can be set to 100 s, 200 s, 400 s or 800 s with the baud rate select ( bsel [ 0..1 ]) configuration option. the header time can be set to 3t e or 10 t e with the header select (header) config- uration option. there are two different modulation formats available on the rfhcs362 that can be set using the modulation select (mod) configuration option: ? pulse width modulation (pwm) ? manchester encoding modulation formats are shown in figure 3-3 and figure 3-4. code word data formats are shown in figure 3-6. figure 3-2: code word transmission sequence figure 3-3: pulse width mo dulation transmission format figure 3-4: manchester transmission format header encrypt fixed guard 1 code word preamble encrypt preamble header logic "1" guard time 31 t e encrypted portion fixed code portion logic "0" preamble 3/10 header t e t e t e t e 1 16 t bp guard preamble header encrypted fixed code 1 2 start bit stop bit time portion portion 16 bit 0 bit 1 bit 2 logic "0" logic "1" t e t e t bp
rfhcs362g/362f ds41189b-page 14 ? 2011 microchip technology inc. 3.1.1 code hopping data the hopping portion is calculated by encrypting the counter, discrimination value and function code with the encoder key (key). the counter is 16 bits wide. the discrimination value is 10 bits wide. there are 2 coun- ter overflow bits (ovr) that are cleared when the coun- ter wraps to 0. the rest of the 32 bits are made up of the function code also known as the button inputs. 3.1.2 fixed code data the 32 bits of fixed code consist of 28 bits of the serial number (ser) and another co py of the function code. this can be changed to contain the whole 32-bit serial number with the ex tended serial number (xser) con- figuration option. 3.1.3 minimum code words mtx[0..1] configuration bits selects the minimum number of code words that wi ll be transmitted. if the button is released after 1.6 s (or greater) and mtx code words have been transmitted, the code word being transmitted will be terminated. the possible values are: 00 - 1 01 - 2 10 - 4 11 - 8 3.1.4 status information the status bits will always contain the output of the low voltage detector (v low ), the cyclic redundancy check (crc) bits (or time bits depending on ctsel) and the button queue information. 3.1.4.1 low voltage detector status (v low ) the output of the low voltage detector is transmitted with each code word. if v dd drops below the selected voltage, a logic ? 1 ? will be transmitted. the output of the detector is sampled before each code word is transmit- ted.
? 2011 microchip technology inc. ds41189b-page 15 rfhcs362g/362f 3.1.4.2 button queue information (queue) the queue bits indicate a button combination was pressed again within 2 s after releasing the previous activation. queuing or repe ated pressing of the same buttons (or button combination) is detected by the rfhcs362 button debouncing circuitry. the queue bits are added as the last two bits of the standard code word. the queue bits are a 2-bit counter that does not wrap. the c ounter value starts at ? 00b? and is incremented if a button is pushed within 2 s of the previous button press. the current code word is ter- minated when the buttons are queued. this allows additional functionality for repeated button presses. the button inputs are sampled every 6.4 ms during this 2 s period. 00 - first activation 01 - second activation 10 - third activation 11 - from fourth activation on 3.1.4.3 time bits the time bits (figure 3-5) indicate the duration that the inputs were activated: 00 - immediate 01 - after 0.8 s 10 - after 1.6 s 11 - after 2.4 s the time bits are increm ented every 0.8 s and will not wrap once it reaches ? 11 ?. time information is alternative to the crc bits availabil- ity and is selected by the ctsel configuration bit. figure 3-5: time bits operation 3.1.4.4 cyclic redu ndancy check (crc) the crc bits are calculated on the 65 previously trans- mitted bits. the decoder can use the crc bits to check the data integrity before processing starts. the crc can detect all single bit errors and 66% of double bit errors. the crc is computed as follows: equation 3-1: crc calculation and with and di n the nth transmission bit 0 n 64 t td time data = one code word time bits = 00 time bits set internally to 01 time bits actually output time bits set internally to 10 time bits actually output 0 s 0.8 s 1.6 s 2.4 s s[3210] crc 1 [] n1 + crc 0 [] n di n = crc 0 [] n1 + crc 0 [] n di n () crc 1 [] n = crc 1 0 , [] 0 0 = warning: the crc may be wrong when the battery voltage is near the selected v low trip point. this may happen because v low is sam- pled twice each transmission, once for the crc calculation and once when v low is transmitted. v dd tends to move slightly dur- ing a transmission which could lead to a dif- ferent value for v low being used for the crc calculation and the transmission. work around: if the crc is incorrect, recalculate for the opposite value of v low .
rfhcs362g/362f ds41189b-page 16 ? 2011 microchip technology inc. figure 3-6: code word data format transmission direction lsb first fixed portion (32 bits) que 2 bits crc 2 bits v low 1-bit serial number (32 bits) q1 q0 c1 c0 but 4 bits counter overflow 2 bits disc 10 bits synchronization 16 bits counter 15 0 s2 s1 s0 s3 ovr1 ovr0 encrypted portion (32 bits) with xser = 1, ctsel = 0 status information (5 bits) fixed portion (32 bits) que 2 bits time 2 bits v low 1-bit serial number (28 bits) q1 q0 t1 t0 s2 s1 s0 s3 with xser = 1, ctsel = 1 status information (5 bits) but 4 bits but 4 bits counter overflow 2 bits disc 10 bits synchronization 16 bits counter 15 0 s2 s1 s0 s3 ovr1 ovr0 encrypted portion (32 bits) fixed code portion (32 bits) que 2 bits crc 2 bits v low 1-bit serial number (28 bits) q1 q0 c1 c0 s2 s1 s0 s3 status information (5 bits) but 4 bits but 4 bits counter overflow 2 bits disc 10 bits synchronization 16 bits counter 15 0 s2 s1 s0 s3 ovr1 ovr0 encrypted portion (32 bits) with xser = 0, ctsel = 0 fixed portion (32 bits) que 2 bits time 2 bits v low 1-bit serial number (32 bits) q1 q0 t1 t0 but 4 bits counter overflow 2 bits disc 10 bits synchronization 16 bits counter 15 0 s2 s1 s0 s3 ovr1 ovr0 encrypted portion (32 bits) status information (5 bits) with xser = 0, ctsel = 1
? 2011 microchip technology inc. ds41189b-page 17 rfhcs362g/362f 3.2 led output the led pin will be driven low periodically while the rfhcs362 is transmitting data to power an external led. the duty cycle (t ledon /t ledoff ) can be selected between two possible values by the configuration option (led). figure 3-7: led operation (led = 1) the same configuration option determines whether when the v dd voltage drops below the selected v low trip point the led will blink only once or stop blinking. figure 3-8: led operation (led = 0) 3.3 dual encoder operation the rfhcs362g/362f contains two encryption keys (for example derived from two different manufacturer?s codes), but only one serial number, one set of dis- crimination bits, one 16-bit synchronization counter and a single 60-bit seed value. for this reason the rfhcs362g/362f can be used as an encoder in multi- ple (two) applications as far as they share the same configuration: transmission format, baud rate, header and guard settings. the shift input pin (multiplexed with the led output) is used to select between the two encryption keys. a logic 1 on the shift input pin selects the first encryp- tion key. a logic 0 on the shift input pin will select the second encryption key. figure 3-9: using dual encoder operation note: when the rfhcs362 encoder is used as a dual encoder the led pin is used as a shift input (figure 3-9). in such a configuration the led is always on during transmission. to keep power consumption low, it is recommended to use a series resistor of relatively high value. v low information is not available when using the second encryption key. s[3210] led v dd > v low t ledon = 25 ms t ledoff led v dd < v low t ledon t ledoff = 500 ms led v dd < v low s[3210] led v dd > v low t ledon t ledoff t ledon = 200 ms t ledoff = 800 ms v dd v dd data v ss shift 1 k led /shift
rfhcs362g/362f ds41189b-page 18 ? 2011 microchip technology inc. figure 3-10: seed code word format 3.4 seed code word data format a seed transmission transmits a unencrypted code word that consists of 60 bits of fixed data that is stored in the eeprom. this can be used for secure learning of encoders or whenever a fixed code transmission is required. the seed code word further contains the function code and the status information (v low , crc and queue) as configured for normal code hopping code words. the seed code word format is shown in figure 3-10. the function code for seed code words is always ? 1111b ?. seed code words can be configured as follows: ? enabled permanently. ? disabled permanently. ? enabled until the synchronization counter is greater than 7fh, this configuration is often referred to as limited seed . ? the time before the seed code word is transmitted can be set to 1.6 s or 3.2 s, this configuration is often referred to as delayed seed . when this option is selected, the rfhcs362 will transmit a code hopping code word for 1.6 s or 3.2 s, before the seed code word is transmitted. 3.4.1 seed options the button combination ( s[3210] ) for transmitting a seed code word can be selected with the seed and seedc ( seed [ 0..1 ] and seedc ) configuration options as shown in table 3-1 and table 3-2: table 3-1: seed options (seedc = 0) table 3-2: seed options (seedc = 1) example a): selecting seedc = 1 and seed = 11 : makes seed transmission available every time the combination of buttons s3 and s0 is pressed simulta- neously, but delayed seed mode is not available. example b): selecting seedc = 0 and seed = 01 : makes seed transmission available only for a limited time (only up to 128 times). the combination of buttons s2 and s0 produces an immediate transmission of the seed code. pressing and holding for more than 1.6 seconds the s0 button alone produces the seed code word transmission (delayed seed). transmission direction lsb first fixed portion que (2 bits) crc (2 bits) v low (1-bit) seed with quen = 1 but (4 bits) (9 bits) seed code (60 bits) q1 q0 c1 c0 11 11 seed 1.6 s delayed seed seed s[3210] s[3210] 00 - - 01 0101* 0001* 10 0101 0001 11 0101 - note: *limited seed seed 3.2 s delayed seed seed s[3210] s[3210] 00 - - 01 1001* 0011* 10 1001 0011 11 1001 - note: *limited seed
? 2011 microchip technology inc. ds41189b-page 19 rfhcs362g/362f 3.5 rf enable and transmitter interface the s3/rfen out pin of the rfhcs362 can be config- ured to function as an rf enable output signal. this is selected by the rf enable output (rfen) configura- tion option as described in section 4.5.13. when enabled, this pin will be driven high before data is transmitted through the data pin. the rfen out and data pins are synchronized to interface with the transmitter. figure 3-11 shows the start-up sequence. a button is debounced and the eeprom counter advanced dur ing the power-up delay (t pu ). then the rfen out pin goes high to enable the transmitter. the data output is delayed to give the transmitter crystal oscillator and pll time to startup (t pll ). the rfen out signal will go low one guard time after the end of the last code word. when the rf enable output is selected, the s3 pin can still be used as a button input. however, only minimum code words will be transmitted. an alternative solution for more than three push buttons can be the switching diode circuit described in section 1.2. in typical implementations of the rfhcs362g/362f, the encoder rfen out pin is connected to the transmitter rfen in pin. figure 3-11: pll interface s[3210] rfen out data t pll guard time 1st code word t g button press button release 2nd code word t pu
rfhcs362g/362f ds41189b-page 20 ? 2011 microchip technology inc. 4.0 eeprom memory organization the rfhcs362g/362f contains 288 bits (18 x 16-bit words) of eeprom memory (table 4-1). this eeprom array is used to store the encryption key information and synchronization value. further descriptions of the memory array is given in the follow- ing sections. table 4-1: eeprom memory map 4.1 key_0 - key_3 (64-bit encryption key) the 64-bit encryption key is used to create the encrypted message. this key is calculated and pro- grammed during production using a key generation algorithm. the key generation algorithm may be differ- ent from the k ee l oq algorithm. inputs to the key gen- eration algorithm are typically the transmitter?s serial number and the 64-bit manufacturer?s code. while the key generation algorithm supp lied from microchip is the typical method used, a user may elect to create their own method of key generation. 4.2 sync (synchronization counter) this is the 16-bit synchronization value that is used to create the hopping code for transmission. this value will be incremented after every transmission. 4.3 seed_0, seed_1, seed_2, and seed 3 (seed word) this is the four word (60 bits) seed code that will be transmitted when seed transmission is selected. this allows the system designer to implement the secure learn feature or use this fixed code word as part of a dif- ferent key generation/tracki ng process or purely as a fixed code transmission. 4.4 serial_0, serial_1 (encoder serial number) serial_0 and serial_1 are the lower and upper words of the device serial number, respectively. there are 32 bits allocated for the serial number and a select- able configuration bit determines whether 32 or 28 bits will be transmitted. the serial number is meant to be unique for every transmitter. word address field description 0 key1_0 64-bit encryption key1 (word 0) lsb 1 key1_1 64-bit encryption key1 (word 1) 2 key1_2 64-bit encryption key1 (word 2) 3 key1_3 64-bit encryption key1 (word 3) msb 4 key2_0 64-bit encryption key2 (word 0) lsb 5 key2_1 64-bit encryption key2 (word 1) 6 key2_2 64-bit encryption key2 (word 2) 7 key2_3 64-bit encryption key2 (word 3) msb 8 seed_0 seed value (word 0) lsb 9 seed_1 seed value (word 1) 10 seed_2 seed value (word 2) 11 seed_3 seed value (word 3) msb 12 config_0 configuration word (word 0) 13 config_1 configuration word (word 1) 14 serial_0 serial number (word 0) lsb 15 serial_1 serial number (word 1) msb 16 sync synchronization counter 17 res reserved ? set to zero note: upper four significant bits of seed_3 con- tains extra configuration information (see table 4-5).
? 2011 microchip technology inc. ds41189b-page 21 rfhcs362g/362f table 4-2: config_0 4.5 configuration words there are 36 configuration bits stored in the eeprom array. they are used by the device to determine trans- mission speed, format, delays and guard times. they are grouped in three configuration words: config_0 , config_1 and the upper nybble of the seed_3 word. a description of each of the bits follows this section. 4.5.1 osc the internal oscillator can be tuned to 10%. ( 0000 selects the nominal value, 1000 the fastest value and 0111 the slowest). when programming the device, it is the programmer?s responsibility to determine the opti- mal calibration value. 4.5.2 vlow[0..2] the low voltage threshold can be programmed to be any of the values shown in table 4-2. 4.5.3 bsel[0..1] the basic timing element t e , determines the actual transmission baud rate. this translates to different code word lengths depending on the encoding format selected (manchester or pwm), the header length selection and the guard time selection, from approxi- mately 40 ms up to 220 ms. refer to table 4-2 for bit rate configuration. refer to figure 10-3 through figure 10-6 for code word timing. 4.5.4 mtx[0..1] mtx selects the minimum number of code words that will be transmitted. a minimu m of 1, 2, 4 or 8 code words will be transmitted. bit address field description values 0 osc_0 oscillator adjust 0000 - nominal 1000 - fastest 0111 - slowest 1 osc_1 2 osc_2 3 osc_3 4 vlow_0 v low select nominal values 5 vlow_1 000 - 2.0v 001 - 2.1v 010 - 2.2v 011 - 2.3v 100 - 4.0v 101 - 4.2v 110 - 4.4v 111 - 4.6v 6 vlow_2 7 bsel_0 bit rate select 00 - t e = 100 s 01 - t e = 200 s 10 - t e = 400 s 11 - t e = 800 s 8 bsel_1 9 mtx_0 minimum number of code words 00 - 1 01 - 2 10 - 4 11 - 8 10 mtx_1 11 guard_0 guard time select 00 - 0 ms (1 t e ) 01 - 6.4 ms + 2 t e 10 - 25.6 ms + 2 t e 11 - 76.8 ms + 2 t e 12 guard_1 13 timout_0 time-out select 00 - no time-out 01 - 0.8 s to 0.8 s + 1 code word 10 - 3.2 s to 3.2 s + 1 code word 11 - 25.6 s to 25.6 s + 1 code word 14 timout_1 15 ctsel ctsel 0 = time bits 1 = crc bits note: if mtx and bsel settings in combination require a transmission sequence to exceed the timout setting, timout will take priority.
rfhcs362g/362f ds41189b-page 22 ? 2011 microchip technology inc. table 4-3: config_1 4.5.5 guard the guard time between code words can be set to 0 ms, 6.4 ms, 25.6 ms and 76.8 ms. if during a series of code words, the output changes from hopping code to seed the guard time will increase by 3 x t e . 4.5.6 timout[0..1] the transmission time-out can be set to 0.8 s, 3.2 s, 25.6 s or no time-out. after the time-out period, the encoder will stop transmission and enter a low power shutdown mode. 4.5.7 disc[0..9] the discrimination bits are used to validate the decrypted code word. the discrimination value is typi- cally programmed with the 10 least significant bits of the serial number or a fixed value. 4.5.8 ovr[0..1] the automatically incrementing synchronization coun- ter is at the core of generating the varying code. since the counter is limited to 16 bits, it overflows after 65536 increments, after which the code hopping sequence repeats. in practice, this allows 20+ operations per day for ten years before repeati ng the sequence. in addi- tion, two overflow bits allow the sequence to be extended further. the feature is enabled by setting to logical ?1? the two overflow bits ovl0 and ovl1. the overflow bits form part of the encrypted transmission, and therefore can be exami ned by receiver firmware. table 4-4 shows how the overflow bits act when they are set to one during initial device configuration. table 4-4: as can be seen from the table, the counter is effectively extended by one bit, that is ovl0. in addition, ovl1 provides indication of the second counter overflow. after the second overflow, ovl0 and ovl1 remain zero, providing permanent evidence of the first and second overflow events. bit address field description values 0 disc_0 discrimination bits disc [ 9:0 ] 1 disc_1 2 disc_2 ... ... 8 disc_8 9 disc_9 10 ovr_0 overflow ovr [ 1:0 ] 11 ovr_1 12 xser extended serial number 0 - disable 1 - enable 13 seedc seed control 0 = seed transmission on: s[3210] = 0001 (delay 1.6 s) s[3210] = 0101 (immediate) 1 = seed transmission on: s[3210] = 0011 (delay 3.2 s) s[3210] = 1001 (immediate) 14 seed_0 seed options 00 - no seed 01 - limited seed (permanent and delayed) 10 - permanent and delayed seed 11 - permanent seed only 15 seed_1 sync. counter ovl0 ovl1 no overflow 0-ffffh 11 first overflow 2nd 0-ffffh 01 second overflow third 0-ffffh 00 subsequent overflows 0 0
? 2011 microchip technology inc. ds41189b-page 23 rfhcs362g/362f 4.5.9 xser if xser is enabled a 32-bit se rial number is transmit- ted. if xser is disabled a 28-bit serial number and a 4-bit function code are transmitted. 4.5.10 seed[0..1] the seed value which is transmitted on key combina- tions ( 0011 ) and ( 1001 ) can be disabled, enabled or enabled for a limited number of transmissions deter- mined by the initial counter value. in limited seed mode, the device will output the seed if the sync counter (section 4.2) is from 00hex to 7fhex. for a counter higher than 7f, a normal hopping code will be output. 4.5.11 seedc seedc selects between se ed transmission on 0001 and 0101 ( seedc = 0 ) and 0011 and 1001 ( seedc = 1 ). the delay before seed transmission is 1.6 s for ( seedc = 0 ) and 3.2 s for ( seedc = 1 ). table 4-5: seed_3 note: whenever a seed code word is output, the 4 function bits (figure 3-10) will be set to all ones [ 1,1,1,1 ]. bit address field description values 0 seed_48 seed most significant word ? 1 seed_49 2 seed_50 ... ... 9 seed_57 10 seed_58 11 seed_59 12 led led output timing 0 = v bot >v low led blink 200/800 ms v bot v low led blink 25/500 ms v bot < v low led blink once 13 mod modulation format 0 = pwm 1 = manchester 14 rfen rf enable/s3 multiplexing 0 - enabled (s3 only sensed 2 seconds after the last but- ton is released) 1 - disabled (s3 same as other s inputs) 15 header pwm header length 0 = short header, t h = 3 x t e 1 = standard header, t h = 10 x t e
rfhcs362g/362f ds41189b-page 24 ? 2011 microchip technology inc. 4.5.12 header when pwm mode is selected the header length (low time between preamble and data bits start) can be set to 10 x t e or 3 x t e . the 10 x t e mode is recommended for compatibility with previous k ee l oq encoder mod- els. in manchester mode, t he header length is fixed and set to 4 x t e . 4.5.13 rfen rfen selects whether the rfen output is enabled or disabled. if enabled, s3 is only sampled 2 s after the last button is released and at the start of the first trans- mission. if disabled s3 functions the same as the other s inputs. for typical implementation of the rfhcs362g/ 362f the rfen bit = 0. 4.6 synchronous mode in synchronous mode, the code word can be clocked out on data using s2 as a clock. to enter synchro- nous mode, s2 must be taken high and then data and s0 or s1 are taken high. after synchronous mode is entered, data and s2 must be taken low. the data is clocked out on data on every falling edge of s2. auto-shutoff timer is not disabled in synchronous mode. refer to figure 4-1 and figure 4-2. figure 4-1: synchronous transmission mode figure 4-2: code word organization (synchronous transmission mode) ?01,10,11? data s2 s0 or s1 t ps t ph 1 t ph 2 t = 50ms preamble header data rfen t rfon 35 pulses on s2 queue (2 bits) crc (2 bits) vlow (1-bit) button status s2 s1 s0 s3 serial number (28 bits) button status s2 s1 s0 s3 disc+ ovr (12 bits) sync counter (16 bits) 69 data bits transmitted lsb first. lsb msb fixed portion encrypted portion
? 2011 microchip technology inc. ds41189b-page 25 rfhcs362g/362f 5.0 programming the rfhcs362g/362f when using the rf hcs362g/362f in a system, the user will have to program some parameters into the device, including the serial number and the secret key before it can be used. the programming cycle allows the user to input all 288 bits in a serial data stream, which are then stored internally in eeprom. programming will be initiated by forcing the data line high, after the s2 line has been held high for the appropriate length of time (table 10-3 and figure 5-1). after the program mode is entered, a delay must be provided to the device for the automatic bulk write cycle to complete. this will write all locations in the eeprom to an all zeros pattern includ- ing the osc calibration bits. the device can then be programmed by clocking in 16 bits at a time, using s2 as the clock line and data as the data in-line. after each 16-bit word is loaded, a pro- gramming delay is required for the internal program cycle to complete. this delay can take up to twc. at the end of the programming cycle, the device can be veri- fied (figure 5-2) by re ading back the eeprom. read- ing is done by clocking the s2 line and reading the data bits on data. for security reasons, it is not possible to execute a verify function without first programming the eeprom. a verify operation can only be done once, immediately following the program cycle . figure 5-1: programming waveforms figure 5-2: verify waveforms note: to ensure that the device does not accidentally enter programming mode, data should never be pulled high by the circuit connected to it. special care should be taken when driving circuits other than the rfen in . data enter program mode (data) (clock) note 1: unused button inputs to be held to gr ound during the entire programming sequence. bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 bit 16 bit 17 t ph 1 t pbw t ps repeat for each word (18 times) t ph 2 t clkh t clkl t wc t ds s2 (s3) data for word 0 (key_0) data for word 1 t dh 2: the v dd pin must be taken to ground after a program/verify cycle. data (clock) (data) note: if a verify operation is to be done, then it must imm ediately follow the program cycle. end of programming cycle beginning of verify cycle bit 1 bit 2 bit 3 bit 15 bit 14 bit 16 bit 17 bit286 bit287 t wc data from word 0 t dv s2 (s3) bit 0 bit287 bit286
rfhcs362g/362f ds41189b-page 26 ? 2011 microchip technology inc. 6.0 uhf ask/fsk transmitter 6.1 transmitter operation the transmitter is a fully integrated uhf ask/fsk transmitter consisting of crystal oscillator, phase- locked loop (pll), open-collector differential-output power amplifier (pa), and mo de control logic. external components consist of bypass capacitors, crystal, and pll loop filter. the rfhcs362g is capable of amplitude shift keying (ask) modulation. the RFHCS362F is capable of ask or frequency shift keying (fsk) mod- ulation by employing an internal fsk switch to pull the transmitter crystal via a second load capacitor. figure 2-1 shows the internal structure of the transmit- ter. transmitter connections are independent from the encoder to provide for maximum design flexibility. example application circui ts for ask or fsk modula- tion are presented in section 1.2. the rfhcs362g/362f are radio frequency (rf) emit- ting devices. wireless rf devices are governed by a country?s regulating agency. for example, in the united states it is the federal communications committee (fcc) and in europe it is the european conference of postal and telecommunica tions administrations (cept). it is the responsibility of the designer to ensure that their end product conforms to rules and regulations of the country of use and/or sale. 6.2 supply voltage (v ddrf , v ssrf ) pins v ddrf and v ssrf supply power and ground respectively to the transmitter. these power pins are separate from power supply pins v dd and v ss to the encoder. 6.3 crystal oscillator the transmitter crystal oscillat or is a colpitts oscillator that provides the reference frequency to the pll. it is independent from the encoder oscillator. an external crystal or ac coupled reference signal is connected to the xtal pin. the transmit frequency is fixed and determined by the crystal frequency according to the formula: due to the flexible selection of transmit frequency, the resulting crystal frequency may not be a standard off- the-shelf value. therefore, for some carrier frequencies the designer will have to c onsult a crystal manufacturer and have a custom crystal manufactured. crystal parameters are listed in table 6-1. for background information on crystal selection see application note an588, pic ? microcontroller oscillator design guide, and an826 crystal oscillator basics and crystal selec- tion for rfpic? and pic mcu devices. the crystal oscillator start time (t on ) is listed in table 10-7, transmitter ac characteristics. table 6-1: crystal parameters rf devices require correct board level implementa- tion in order to meet regulatory requirements. layout considerations are listed at the end of each subsec- tion. it is best to place a ground plane on the pcb to reduce radio frequency emissions and cross talk. layout considerations - provide low impedance power and ground traces to minimize spurious emis- sions. a two-sided pcb with a ground plane on the bottom layer is highly recommended. separate bypass capacitors should be connected as close as possible to each of the supply pins v dd and v ddrf . connect v ss and v ssrf to the ground plane using separate pcb vias. do not share a pcb via with mul- tiple ground traces. 32 = xtal transmit f f sym characteristic min max units conditions f xtal crystal frequency 9.69 15 mhz parallel resonant mode c l load capacitance 10 15 pf c o shunt capacitance ? 7 pf esr equivalent series resistance ? 60 these values are for design guidance only.
? 2011 microchip technology inc. ds41189b-page 27 rfhcs362g/362f 6.3.1 crystal oscillator ask operation the rfhcs362g/362f crystal oscillator can be config- ured for ask operation. fi gure 6-1 shows an example ask circuit. capacitor c1 trims the crystal load capacitance to the desired circuit load capacitance and places the crystal on the desired frequency. figure 6-1: example ask external crystal circuit table 6-2: xtal osc approximate fr eq. vs. capacitance (ask mode) (1) xtal rfhcs362g/ 362f x1 c1 c1 predicted frequency (mhz) ppm from 13.55 mhz transmit frequency (mhz) (32 * f xtal ) 22 pf 13.551438 +106 433.646 39 pf 13.550563 +42 433.618 100 pf 13.549844 -12 433.595 150 pf 13.549672 -24 433.5895 470 pf 13.549548 -33 433.5856 1000 pf 13.549344 -48 433.579 note 1: standard operating conditions ( unless otherwise stated) t a = 25c, rf en = 1, v ddrf = 3v, f xtal = 13.55 mhz
rfhcs362g/362f ds41189b-page 28 ? 2011 microchip technology inc. 6.3.2 crystal oscillator fsk operation the RFHCS362F crystal oscillator can be configured for fsk operation. figure 6-2 shows an example fsk cir- cuit. capacitors c1 and c2 achieve fsk modulation by pulling the crystal. when data fsk = 1, fskout is high-impedance effectively coupling only capacitor c1 to the crystal and the resulting transmit frequency equals f max . when data fsk = 0, fskout is grounded to v ssrf and will parallel capacitor c2 with c1. the resulting transmit frequency will equal f min . selecting the appropriate values for c1 and c2 sets the center frequency and frequency deviation. capacitor c1 sets f max and capacitors c1 and c2 in parallel set f min . the graph in figure 6-3 illustrates this relation- ship. the transmit center frequency f c is defined as: the frequency deviation of the transmit frequency is defined as: table 6-3: typical transmit center frequency and frequency deviation (fsk mode) (1) figure 6-2: example fsk external crystal circuit figure 6-3: load capacitance versus change in transmitted frequency layout considerations - avoid parallel traces in order to reduce circuit stray capacitance. keep traces as short as possible. isolate components to prevent cou- pling. use ground traces to isolate signals. 2 min max f f f c + = f f f ? = c2 = 1000 pf c2 = 100 pf c2 = 47 pf c1 (pf) freq (mhz) / dev (khz) freq (mh z) / dev (khz) freq (mhz) / dev (khz) 22 433.612 / 34 433.619 / 27 433.625 / 21 33 433.604 / 25 433.610 / 19 433.614 / 14 39 433.598 / 20 433.604 / 14 433.608 / 10 47 433.596 / 17 433.601 / 11.5 433.604 / 8 68 433.593 / 13 433.598 / 9 433.600 / 5.5 100 433.587 / 8 ? ? note 1: standard operating conditions ( unless otherwise stated) t a = 25c, rf en = 1, v ddrf = 3v, f xtal = 13.55 mhz xtal RFHCS362F x1 c1 c2 fskout frequency (mhz) fmax fmin c1 c1||c2 data fsk = 1 data fsk = 0 load capacitance (pf)
? 2011 microchip technology inc. ds41189b-page 29 rfhcs362g/362f 6.4 clock output (clkout) the crystal oscillator feeds a divide-by-four circuit that provides a clock output at the clkout pin. clkout is slew-rate limited in or der to keep spurious signal emissions as low as possible. the voltage swing (v clkout ) depends on the capacitive loading (c load ) on the clkout pin (2 v pp at 5 pf). 6.5 phase-locked loop (pll) the pll consists of a phase-frequency detector (pfd), charge pump, volt age-controlled oscillator (vco), and fixed divide-by-32 divider. an external loop filter is connected to pin lf . the loop filter controls the dynamic behavior of the pll, primarily lock time and spur levels. the application determines the loop filter requirements. the rfhcs362 employs a charge pump pll that offers many advantages over the classical voltage phase detector pll: infinite pull-in range and zero steady state phase error. the charge pump pll allows the use of passive loop filters that are lower cost and minimize noise. charge pump plls have reduced flicker noise thus limiting phase noise. ma ny of the classical texts on plls do not cover this type of pll, however, today this is the most common type of pll. this data sheet briefly covers the general terms and design requirements for the rfpic. detailed pll desig n and operation is beyond the scope of this data sheet. for more information, the designer is referred to " pll performance, simulation, and design ," second edition by dean banerjee isbn 0970820704. banerjee covers charge pump plls and loop filter selection. the loop filter has a major impact on lock time and spur levels. lock time is the time it takes the pll to lock on frequency. when the pll is first powered on or is changing frequencies, no data can be transmitted. lock time must be considered before data transmission can begin. in addition to pll lock time, the designer must take into account the cr ystal oscillator start time of approximately 1 ms. see sect ion 6.3 for more informa- tion about the crystal oscillator. reference spurs occur at the carrier frequency plus and minus integer multi- ples of the reference frequency. phase noise refers to noise generated by the pll. spur levels and phase noise can increase the signal to noise ratio (snr) of the system and mask or degrade the transmitted sig- nal. the first order effect on pll performance is loop band- width. loop bandwidth ( c ) is defined as the point where the open loop phase transfer function equals 0 db. selecting a small loop bandwidth results in lower spur levels but slower lock time. selecting a larger loop bandwidth results in a faster lock time but higher spur levels. second order effects on pll performance is phase margin ( ) and damping factor ( ). phase margin is a measure of pll stability. choosing a phase margin that is too low will result in pll instability. choosing a higher phase margin results in less ringing and faster lock time at the expense of higher spur levels. loop filters are typically designed for a total phase margin between 30 and 70 degrees. the aim of the designer is to choose a loop bandwidth and phase margin that gives the fast- est possible lock time and meets the spur level require- ments of the application. damping factor governs the second order transient response that determines the shape of the exponential envelope of the natural fr equency. the natural fre- quency, also called ringing frequency, is the frequency of the vco steering voltag e as the pll settles. lock time is proportional to damping factor and inversely proportional to loop bandwidth. the application determines the loop filter component requirements. for example, if the transmit frequency selected is near band edges or restricted bands, spur levels must be reduced to meet regulatory require- ments. however, this will be at the expense of lock time. for an fsk application, a larger damping factor ( ? 1.0) is desired so that there is less overshoot in the keying of fsk. for an ask application, a damping fac- tor = 0.707 results in less settling time and near opti- mum noise performance. figure 6-4 shows an example passive second order loop filter circuit. table 6-4 gives example loop filter val- ues for a crystal frequency of 13.56 mhz and transmit frequency of 433.92 mhz. table 6-5 gives example loop filter values for a crystal frequency of 9.84375 mhz and transmit frequency of 315 mhz. layout considerations - shield each side of the clock output trace with ground trac es to isolate the clk- out signal and reduce coupling. layout considerations - keep traces short and place loop filter components as close as possible to the lf pin.
rfhcs362g/362f ds41189b-page 30 ? 2011 microchip technology inc. figure 6-4: example loop filter circuit table 6-4: example loop filter values for transmit frequency = 433.92 mhz (1) table 6-5: example loop filter valu es for transmit frequency = 315 mhz (1) lf rfhcs362g/362f r1 c1 c 2 c1 c2 r1 loop bw fn (natural freq in hz) phase margin (not counting sampling delay) 2nd order damping factor calculated lock time 0.01 uf 390 pf 680 165 khz 64 khz 65 deg 1.37 47 s 3900 pf 100 pf 1.5k 360 khz 103 khz 63 deg 1.89 29 s 1500 pf 47 pf 2.7k 610 khz 166 khz 55 deg 2.10 18 s 1000 pf 18 pf 4.7k 1.05 mhz 203 khz 50 deg 3.0 15 s note 1: standard operating conditions ( unless otherwise stated) t a = 25c, rf en = 1, v ddrf = 3v. c1 c2 r1 loop bw fn (natural freq in hz) phase margin (not counting sampling delay) 2nd order damping factor calculated lock time 3900 pf 390 pf 680 190 khz 112 khz 55 deg 0.94 27 s 3900 pf 680 pf 680 175 khz 112 khz 47 deg 0.94 27 s 3900 pf 1000 pf 680 155 khz 112 khz 39 deg 0.94 27 s note 1: standard operating conditions ( unless otherwise stated) t a = 25c, rf en = 1, v ddrf = 3v.
? 2011 microchip technology inc. ds41189b-page 31 rfhcs362g/362f 6.6 power amplifier the pll output feeds the power amplifier (pa). the open-collector differential output (ant1, ant2) can be used to drive a loop antenna directly or converted to single-ended output via an impenance matching net- work or balanced-to-unbalanced (balun) transformer. pins ant1 and ant2 are open-collector outputs and must be pulled-up to v ddrf through the load. the differential output of the pa should be matched to an impedance of 800 to 1000 . failure to match the impedance may cause excessive spurious and har- monic emissions. for more information see application note an831, matching small loop antennas to rfpic devices. the transmit output power can be adjusted in six dis- crete steps from +2 dbm to -12 dbm by varying the volt- age (v ps ) at the ps/data ask pin. figure 6-5 shows an example voltage divider network for ask operation and figure 6-6 for fsk operation. for fsk operation, the ps/data ask pin only serves as a power select (ps) pin. an internal 20 a current source pushes current through the ps/data ask pin resulting in a voltage drop across resistor r2 at the v ps level selected for transmitter output power. v ps selects the pa bias current. higher transmit power will draw higher current. for ask operation, the function of the ps/data ask pin is to turn the power amplifier (pa) on and off. resistors r1 and r2 form a voltage divider network to apply volt- age v ps for the selected transmitter output power. if maximum transmitter output is desired, the output of a gp0 pin can be connect ed directly to ps/data ask . table 6-6 lists typical values for r1 and r2 for both the ask and fsk modes. . figure 6-5: example ask power select circuit figure 6-6: example fsk power select circuit table 6-6: power select (1) note: ps/data ask is driven low when rfen in = 0. make sure external circuitry on ps/data ask does not conflict by driving the pin high. the encoder data output works because it is low if rfen out is low ps/data ask rfhcs362g/362f r2 r1 data in v ps 20 a to power select circuitry ps/data ask rfhcs362g/362f r2 v ps 20 a to powe r select circuitry transmitter output power (dbm) transmitter operating current (ma) power select (ps) voltage v ps (volts) (2) ask fsk r1 ( )r2 ( ) (3) r2 ( ) +2 11.5 2.0 2400 4700 75k -1 8.6 1.2 6800 4700 56k -4 7.3 0.9 11k 4700 47k -7 6.2 0.7 15k 4700 39k -10 5.3 0.5 24k 4700 27k -12 4.8 0.3 43k 4700 15k -60 <4.8 <0.1 open 4700 4700
rfhcs362g/362f ds41189b-page 32 ? 2011 microchip technology inc. note 1: standard operating conditions ( unless otherwise stated) t a = 25c, rf en = 1, v ddrf = 3v, f transmit = 433.92 mhz 2: v ps is actual voltage on ps/data ask pin. 3: the power select circuitry contains an internal 20 a current source. to ensure that the transmitter output power is at the minimum when transmitting a data ask = 0 (v ssrf ), select the value of resistor r2 such that the voltage drop across it is less than 0.1 volts.
? 2011 microchip technology inc. ds41189b-page 33 rfhcs362g/362f 6.7 mode control logic the mode control logic pin rfen in controls the oper- ation of the transmitte r (table 6-7). when rfen in goes high, the crystal oscillator starts up. the voltage on the lf pin ramps up proportionally to the rf fre- quency. the pll can lock onto the frequency faster than the starting up crystal can stabilize. when the lf pin reaches 0.8v, the rf frequency is close to locked on the crystal frequency. this initiates a 150 micro- second delay to ensure that the pll settles. after the delay, the ps/data ask bias current and power ampli- fier are enabled to start transmitting. when rfen in goes low, the transmitter goes into low power standby mode. the power amplifier is dis- abled, the crystal oscillat or stops, and the ps/data- ask pin is driven low. this will be a conflict if other circuitry drives the ps/data ask pin high while rfen in is low. the encoder data pin is typically the only con- nection to ps/data ask and it always drives data low before rfen out goes low. for most applications the rfen in pin is connected directly to the rfen out pin. the rfen in pin has an internal pull-down resistor. table 6-7: rfen in pin states rf en description 0 transmitter and clkout in standby 1 transmitter and clkout enabled
rfhcs362g/362f ds41189b-page 34 ? 2011 microchip technology inc. 7.0 integrating the rfhcs362g/ 362f into the system use of the rfhcs362g/362f in a system requires a compatible decoder. this decoder is typically a micro- controller with compatible firmware. microchip will pro- vide (via a license agreement) firmware routines that accept transmissions from the rfhcs362g/362f and decrypt the hopping code po rtion of the data stream. these routines provide system designers the means to develop their own decoding system. 7.1 learning a transmitter to a receiver a transmitter must first be 'learned' by a decoder before its use is allowed in the system. several learning strat- egies are possible, figure 7-1 details a typical learn sequence. core to each, the decoder must minimally store each learned transmitter's serial number and cur- rent synchronization counter value in eeprom. addi- tionally, the decoder typically stores each transmitter's unique encryption key. the maximum number of learned transmitters will ther efore be relative to the available eeprom. a transmitter's serial number is transmitted in the clear but the synchronization counter only exists in the code word's encrypted portion. the decoder obtains the counter value by decrypting using the same key used to encrypt the information. the k ee l oq algorithm is a symmetrical block cipher so the encryption and decryp- tion keys are identical and referred to generally as the encryption key. the encoder receives its encryption key during manufacturing. the decoder is programmed with the ability to generate an encryption key as well as all but one required input to the key generation routine; typically the transmitter's serial number. figure 7-1 summarizes a typi cal learn sequence. the decoder receives and authenticates a first transmis- sion; first button press. authentication involves gener- ating the appropriate enc ryption key, decrypting, validating the correct key usage via the discrimination bits and buffering the counter value. a second trans- mission is received and authenticated. a final check verifies the counter values were sequential; consecu- tive button presses. if the learn sequence is success- fully complete, the decoder stores the learned transmitter's serial num ber, current synchronization counter value and appropriate encryption key. from now on the encryption key will be retrieved from eeprom during normal operation instead of recalcu- lating it for each transmission received. certain learning strategies have been patented and care must be take n not to infringe. figure 7-1: typical learn sequence enter learn mode wait for reception of a valid code generate key from serial number use generated key to decrypt compare discrimination value with fixed value equal wait for reception of second valid code compare discrimination value with fixed value use generated key to decrypt equal counters encryption key serial number synchronization counter sequential ? ? ? exit learn successful store: learn unsuccessful no no no yes yes yes
? 2011 microchip technology inc. ds41189b-page 35 rfhcs362g/362f 7.2 decoder operation figure 7-2 summarizes normal decoder operation. the decoder waits until a transmission is received. the received serial number is compared to the eeprom table of learned transmitters to first determine if this transmitter's use is allowed in the system. if from a learned transmitter, the transmission is decrypted using the stored encryption key and authenticated via the discrimination bits for appropriate encryption key usage. if the decryption was valid the synchronization value is evaluated. figure 7-2: typical decoder operation 7.3 synchronization with decoder (evaluating the counter) the k ee l oq technology patent scope includes a sophisticated synchronization technique that does not require the calculation and st orage of future codes. the technique securely blocks invalid transmissions while providing transparent resynchronization to transmitters inadvertently activated aw ay from the receiver. figure 7-3 shows a 3-partition, rotating synchronization window. the size of each window is optional but the technique is fundamental. each time a transmission is authenticated, the intended function is executed and the transmission's synchroni zation counter value is stored in eeprom. from t he currently stored counter value there is an initial "single operation" forward win- dow of 16 codes. if the difference between a received synchronization counter and the last stored counter is within 16, the intended function will be executed on the single button press and the new synchronization coun- ter will be stored. storing the new synchronization counter value effectively rotates the entire synchroniza- tion window. a "double operation" (resynchronization) window fur- ther exists from the sing le operation window up to 32k codes forward of the currently stored counter value. it is referred to as "double operation" because a trans- mission with synchronization c ounter value in this win- dow will require an additional, sequential counter transmission prior to executing the intended function. upon receiving the sequential transmission the decoder executes the intend ed function and stores the synchronization counter valu e. this resynchronization occurs transparently to the user as it is human nature to press the button a second ti me if the first was unsuc- cessful. the third window is a "blocked window" ranging from the double operation window to the currently stored synchronization counter value. any transmission with synchronization counter value within this window will be ignored. this window excludes previously used, perhaps code-grabbed transmissions from accessing the system. ? transmission received does serial number match ? decrypt transmission is decryption valid ? is counter within 16 ? is counter within 32k ? update counter execute command save counter in temp location start no no no no yes yes yes yes yes no and no note: the synchronization method described in this section is only a typical implementation and because it is usually implemented in firmware, it can be altered to fit the needs of a particular system.
rfhcs362g/362f ds41189b-page 36 ? 2011 microchip technology inc. figure 7-3: synchronization window blocked entire window rotates to eliminate use of previously used codes single operation window window (32k codes) (16 codes) double operation (resynchronization) window (32k codes) stored synchronization counter value
? 2011 microchip technology inc. ds41189b-page 37 rfhcs362g/362f 8.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families ? simulators - mplab sim software simulator ? emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstratio n/development boards, evaluation kits, and starter kits 8.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
rfhcs362g/362f ds41189b-page 38 ? 2011 microchip technology inc. 8.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 8.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c comp ilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 8.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 8.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 8.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2011 microchip technology inc. ds41189b-page 39 rfhcs362g/362f 8.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 8.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 8.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 8.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mp lab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connec ted to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
rfhcs362g/362f ds41189b-page 40 ? 2011 microchip technology inc. 8.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the applicatio n. when halted at a break- point, the file registers ca n be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 8.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpor ates an mmc card for file storage and data applications. 8.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstr ation, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, sw itches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
? 2011 microchip technology inc. ds41189b-page 41 rfhcs362g/362f 9.0 electrical characteristics absolute maximum ratings? ambient temperature under bias ................................................................................................. .............-40c to +85c storage temperature ............................................................................................................ .................. -40c to +125c total power dissipation (1) ............................................................................................................................... .....700 mw absolute maximum ratings encoder voltage on v dd with respect to v ss ..............................................................................................................-0.3 to +6.6v max. output current sunk by any i/o pin.............. .......................................................................... ........................20 ma max. output current sourced by any i/o pin........... .......................................................................... ......................20 ma voltage on all other encoder pins with respect to v ss ................................................................... -0.3 v to (v dd + 0.3v) absolute maximum ra tings transmitter voltage on v ddrf with respect to v ssrf ......................................................................................................-0.3 to +7.0v max. voltage on rfen in and data fsk pins with respect to v ssrf ...............................................-0.3 to (v ddrf +0.3v) max. current into rfen in and data fsk pins.............................................................................................-1.0 to 1.0 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) + v ddrf x {i dd rf - i ohrf } + {(v dd rf -v ohrf ) x i ohrf } ? notice: stresses above those listed under "absolute ma ximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
rfhcs362g/362f ds41189b-page 42 ? 2011 microchip technology inc. 10.0 dc characteristics table 10-1: encoder dc characteristics industrial (i): t amb = -40 c to +85 c 2.0v < v dd < 6.3 parameter sym. min. typ. (1) max. unit conditions operating current (avg.) i cc ?0.31.2ma v dd = 6.3v standby current i ccs ?0.11.0 av dd = 6.3v high level input voltage v ih 0.65 v dd ?v dd + 0.3 v v dd = 2.0v low level input voltage v il -0.3 ? 0.15 v dd vv dd = 2.0v high level output voltage v oh 0.7 v dd 0.7 v dd ??vi oh = -1.0 ma, v dd = 2.0v i oh = -2.0 ma, v dd = 6.3v low level output voltage v ol ? ?0.15 v dd 0.15 v dd vi ol = 1.0 ma, v dd = 2.0v i ol = 2.0 ma, v dd = 6.3v rfen pin high drive i rfen 0.5 1.0 1 2.5 3.0 5.0 ma v rfen = 1.4v v dd = 2.0v v rfen = 4.4v v dd = 6.3v led sink current i ledl i ledh 1.0 2.0 3.5 4.5 6.0 7.0 ma ma v led = 1.5v, v dd = 3.0v v led = 1.5v, v dd = 6.3v pull-down resistance; s0-s3 r s 0-3 40 60 80 k v dd = 4.0v pull-down resistance; pwm r pwm 80 120 160 k v dd = 4.0v note 1: typical values are at 25 c.
? 2011 microchip technology inc. ds41189b-page 43 rfhcs362g/362f figure 10-1: power-up and transmit timing table 10-2: power-up and tr ansmit timing requirements (3) v dd = +2.0 to 6.3v industrial(i):t amb = -40 c to +85 c parameter symbol min. typical max. unit remarks transmit delay from button detect t td 26 30 40 ms (note 1) debounce delay t db 18 20 22 ms ? auto-shutoff time-out period (timo=10) t to 23.4 25.6 28.16 s (note 2) button press to rfen t pu 20 26 38 ms ? rfen to code word t pll 246ms ? led on after key press t led 25 ? 45 ms ? time to terminate code word from previous button press t tp ? ? 10 ms ? ? note 1: transmit delay maximum value if the previous transmission was successfully transmitted. 2: the auto-shutoff time-out period is not tested. 3: these values are characterized but not tested s n t db data t td t to code word 1 code word 2 code word 3 code word n t tp button press detect rfen led t pll t led 1 t e code word from previous button press
rfhcs362g/362f ds41189b-page 44 ? 2011 microchip technology inc. table 10-3: programming/ver ify timing requirements figure 10-2: pwm data format (mod = 0) v dd = 5.0 10% 25c 5c parameter symbol min. typical max. unit remarks program mode setup time t ps 3.5 ? 4.5 ms hold time 1 t ph 13.5 ? ? ms hold time 2 t ph 250 ? ? s bulk write time t pbw 4.0 ? ? ms program delay time t prog 4.0 ? ? ms program cycle time t wc 50 ? ? ms clock low time t clkl 50 ? ? s clock high time t clkh 50 ? ? s data setup time t ds 0?? s data hold time t dh 30 ? s data out valid time t dv ??30 s bit 0 bit 1 header bit 30 bit 31 bit 32 bit 33 bit 58 bit 59 fixed portion of transmission encrypted portion guard lsb lsb msb msb s3 s0 s1 s2 v low crc0 crc1 time serial number function code status bit 60 bit 61 bit 62 bit 63 bit 64 bit 65 crc/time bit 66 queue q0 q1 bit 67 bit 68
? 2011 microchip technology inc. ds41189b-page 45 rfhcs362g/362f figure 10-3: pwm format summary (mod=0) figure 10-4: pwm preamble/header format (mod=0) table 10-4: code word transmission timing parameters ? pwm mode (1,3) v dd = +2.0v to 6.3v industrial (i): t amb = -40 c to +85 c bsel value 11 10 01 00 symbol characteristic typical typical typical typical units t e basic pulse element 800 400 200 100 s t bp bit width 3333t e t p preamble duration 31 31 31 31 t e t h header duration (4) 10 10 10 10 t e t c data duration 207 207 207 207 t e t g guard time (2) 27.2 26.4 26 25.8 ms ? total transmit time 220 122 74 50 ms ? data rate 417 833 1667 3334 bps note 1: the timing parameters are not tested but derived from the oscillator clock. 2: assuming guard = 10 option selected in config_0 configuration word. 3: allow for a +/- 10% tolerance on the encoder internal oscillator after calibration. 4: assuming header = 1 option selected in seed_3 configuration word. logic "1" guard time 31 t e encrypted portion fixed code portion logic "0" preamble 3/10 header t e t e t e t e 1 16 t bp 50% duty cycle preamble p1 p16 31xt e 3 or 10xt e header data bits bit 0 bit 1
rfhcs362g/362f ds41189b-page 46 ? 2011 microchip technology inc. figure 10-5: manchester format summary (mod=1) figure 10-6: manchester preamble/header format (mod=1) table 10-5: code word transmission timing parameters?manchester mode (1,3) v dd = +2.0v to 6.3v industrial (i): t amb = -40 c to +85 c bsel value 11 10 01 00 symbol characteristic typical typical typical typical units t e basic pulse element (3) 800 400 200 100 s t bp bit width 2222t e t p preamble duration 31 31 31 31 t e t h header duration 4 4 4 4 t e t c data duration 138 138 138 138 t e t g guard time (2) 26.8 26.4 26 25.8 ms ? total transmit time 166 96 61 43 ms ? data rate 625 1250 2500 5000 bps note 1: the timing parameters are not tested but derived from the oscillator clock. 2: assuming guard = 10 option selected in config_0 configuration word. 3: allow for a +/- 10% tolerance on the encoder internal oscillator after calibration. guard preamble header encrypted fixed code 1 2 start bit stop bit time portion portion 16 bit 0 bit 1 bit 2 logic "0" logic "1" t e t e t bp preamble header 31 x t e 4 x t e bit 0 bit 1 data word transmission p1 p16
? 2011 microchip technology inc. ds41189b-page 47 rfhcs362g/362f table 10-6: transmitter dc characteristics* * these parameters are characterized but not tested. ? data in ?typ? column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: depends on output power selection. see table 6-6. note 2: applies to rf en pin. table 10-7: transmitter ac characteristics* bit * these parameters are characterized but not tested. ? data in ?typ? column is at 3v, 25c unless otherwi se stated. these parameters are for design guidance only and are not tested. note 1: values dependent on pll loop filter values. note 2: t on equals crystal oscillator and pll start-up time. note 3: max fsk data rate requires crystal with a ppropriate motional parameters. see section 6.3. dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c param no. sym characteristic min typ ? max units conditions v ddrf supply voltage 2.2 ? 5.5 v i pdrf power-down current ? 0.05 0.1 arf en = 0 i ddrf supply current 4.8 ? 11.5 ma note 1 v ilrf input low voltage -0.3 ? 0.3 v ssrf v note 2 v ihrf input high voltage 0.7 v ssrf ?v ssrf + 0.3 v note 2 i ilrf input leakage current -1 ? 1 a ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c param no. sym characteristic min typ ? max units conditions f xtal crystal frequency 9.69 ? 15 mhz f transmit transmit frequency 310 ? 440 mhz fixed, set by f xtal f clkout clkout frequency 2.42 ? 3.75 mhz fixed, set by f xtal p o transmit output power -12 ? +2 dbm see table 6-6 f ask ask data rate ? ? 40 kbps f fsk fsk data rate ? ? 20 kbps note 3 p ref reference spurs (1) ?-44? dbm f transmit f xtal p clk clock spurs (1) ?-44? dbm f transmit f clkout p harm harmonic content ? -40 ? dbm 2f transmit , 3f transmit , 4f transmit,... p off spurious output signal ? -60 ? dbm vps 0.1v pn phase noise ? -87 ? dbc/hz f transmit 500 khz k vco vco gain ? 100 ? mhz/v i cp charge pump current ? 260 ? a v clkout clock voltage swing ? 2 ? v pp c load = 5 pf t on start-up time ? 0.9 ? ms note 2
rfhcs362g/362f ds41189b-page 48 ? 2011 microchip technology inc. appendix a: additional information microchip?s secure data products are covered by some or all of the following: code hopping encoder patents issued in european countries and u.s.a. secure learning patents issued in european countries, u.s.a. and r.s.a. revision history revision b (june 2011) ? updated the following sections: development sup- port, the microchip web site, reader response and rfhcs362g/362f product identification system ? added new section appendix a ? minor formatting and text changes were incorporated throughout the document
? 2011 microchip technology inc. ds41189b-page 49 rfhcs362g/362f the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com. under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://micro chip.com/support
rfhcs362g/362f ds41189b-page 50 ? 2011 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41189b rfhcs362g/362f 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2011 microchip technology inc. ds41189b-page 51 rfhcs362g/362f rfhcs362g/362f product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type. part no. x /xx xxx pattern package temperature range device device rfhcs362g: rf code hopping encoder RFHCS362F : rf code hopping encoder rfhcs362gt : rf code hopping encoder (tape & reel) RFHCS362Ft: rf code hopping encoder (tape & reel) temperature range i = -40 c to+85 c package so = 300 mil soic ss = 209 mil ssop pattern special requirements
rfhcs362g/362f ds41189b-page 52 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds41189b-page 53 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip te chnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-234-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature ma y be a violation of the digita l millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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